Design of Baugh-wooley Multiplier using Verilog HDL. Shruti D. Kale, Prof. Gauri N. Zade. India. Abstract: Multiplication represents one of the major holdups in. Adders and Multipliers. Baugh-Wooley Multiplier Design • To illustrate the mathematical transformation which is required, consider 4-bit signed operands X and. This project presents an efficient implementation of a high speed multiplier using the shift and adds method of. Baugh-Wooley Multiplier.

Author: Fenrijind Arashigar
Country: Mali
Language: English (Spanish)
Genre: Career
Published (Last): 11 June 2012
Pages: 473
PDF File Size: 3.35 Mb
ePub File Size: 6.21 Mb
ISBN: 717-4-43148-829-6
Downloads: 41641
Price: Free* [*Free Regsitration Required]
Uploader: Zulkilmaran

Computer arithmetic – algorithms and hardware designs Behrooz Parhami Miltiplier the numbers to be multiplied be A and B. In [6]the authors have proposed a new reversible gate called as HNG gate. The proposed reversible Baugh-Wooley multiplier design requires 16 constant inputs, but the design in [5] [7] – [9] requires 52, 40, 44 and 42 respectively.

Therefore the proposed multiplier cells are evaluated based on the Gate count, Garbage inputs and Garbage outputs. Even though various researches have been done for designing reversible multiplier, this work is the first in the literature to use Baugh-Wooley algorithm using reversible logic. Topics Discussed in This Paper.

Design of Compact Baugh-Wooley Multiplier Using Reversible Logic

The garbage output is the one which is not used for further computations. International Journal on Engineering Science and Technology, 2, Circuits and Systems07Apart from that the reversible logic circuit should use 1 lowest number of reversible gates, 2 lowest number of garbage outputs, 3 lowest number of constant inputs.


Efficient realization of large size two’s complement multipliers using multiplirr blocks in FPGAs. The conclusion of the above discussion is that, it is evident that the proposed reversible Baugh-Wooley multiplier circuit design is better than the existing designs with respect to gate counts, garbage inputs and garbage outputs.

A Fixed-Width Modified Baugh-Wooley Multiplier Using Verilog

The proposed Baugh-Wooley multiplier design requires 20 gates. In the recent years various reversible multiplier designs have been proposed [5] – [9].

World Applied Sciences Journal, 10, HNG gates are used in the second step, Multi operand addition. Out of the five outputs, two outputs Q and R are left unspecified, since these are the garbage outputs. The number of inputs and outputs are three in count; if the first two bits A and B are set, the third bit will be inverted, otherwise all bits will keep on the same value. BaughBruce A.

Showing of 11 references. Feynman Gate FG can be used as a copying gate. To generate the partial products, 16 Peres gates have been used, for 16 one-bit multiplication arrays. The proposed reversible Baugh- Wooley multiplier design produces 48 garbage outputs, but the design in [5] [7] – [9] produces 52, 52, 40 and 49 garbage outputs respectively.


The yellow cells represent the full adder. Tab stop Adder electronics Field-programmable gate array Multiplication. The number of gates, constant inputs and garbage outputs.

Out of this, three outputs are maintained as garbage outputs. Measuring the reversible logic design in terms of number of gates is one of the major factors. Bauhg origin of the reversible computing is the research work done by R. This scenario motivates the study of reversible computing field. Besides, synthesizing reversible logic circuits is much difficult than conventional irreversible logic circuits due to the constraints. In the block diagram shown in Figure 5three types of multipleir are used.

References Publications referenced by this paper. This reversible multiplier cell is useful in building up regularity in the array multipliers.